State-of-the-art personal computers and multimedia devices typically require high speed integrated circuit memory devices to operate efficiently. High speed integrated circuit memory devices now include a family of merged memory/logic (MML) devices. As will be understood by those skilled in the art, such devices include high speed logic and memory circuits on a single integrated circuit chip. Techniques for increasing the speed of memory devices typically include techniques for increasing the speed of writing and reading operations.
Referring now to FIG. 1, a conventional integrated circuit memory device is illustrated. This memory device includes a memory cell 101, a bit line sense amplifier 103 and a column select circuit 105. The memory cell 101 may include an access transistor which has a gate electrode electrically connected to a word line WL. Data can be written to a pair of memory cells or read from a pair of memory cells via a pair of complementary bit lines BL and /BL. Data can also be passed to or from a pair of complementary input/output lines via the column select circuit 105 by applying a logic 1 column select signal (CSL) thereto to turn on the pass transistors therein.
Complementary write data can be provided to the input/output lines IO and /IO by a data input buffer 109 and an I/O driver and precharge circuit 107. The I/O driver and precharge circuit 107 is responsive to a precharge signal PIOPR and a driver signal PDT. In particular, when the precharge signal PIOPR is set to a logic 1 potential, the complementary input/output lines IO and /IO are equalized at a desired potential (e.g., Vdd or Vdd/2), however, when the driver signal PDT is set to a logic 1 potential, data is passed from the data-in port (Din) to the input/output lines IO and /IO. During a reading operation, data can be provided to a data-out port (Dout) via an I/O sense amplifier 111 and data output buffer 113.
Referring now to FIG. 2, performance of a read operation on the memory device of FIG. 1 may include the steps of generating a logic 1 write enable signal (WEB) and a logic 0 column address strobe (CASB) pulse at a leading edge of a clock signal (CLK). Then, prior to generation of a logic 1 column select signal (CSL), the precharge signal PIOPR can be generated at a logic 1 potential to cause the input/output lines IO and /IO to be precharged. After the input/output lines have been sufficiently precharged, the precharge signal PIOPR is reset to a logic 0 potential and the column select signal CSL is set to a logic 1 potential (enabled). After the column select signal CSL has been enabled, data from a pair of complementary memory cells is passed from the complementary bit lines BL and /BL to the input/output lines IO and /IO, as illustrated.
Next, the performance of a write operation may include the steps of generating a logic 0 write enable (WEB) pulse and a logic 0 column address strobe (CASB) pulse at the leading edge of the clock signal CLK. Then, while the column select signal CSL is maintained at a logic 0 potential, the precharge signal PIOPR is set to a logic 1 potential to precharge the input/output lines IO and /IO. Next, the driver signal PDT and column select signal CSL are simultaneously set to a logic 1 potentials so that input data can be passed from the driver circuit 107 to the complementary bit lines BL and /BL (via the input/output lines IO and /IO and the column select circuit 105). Unfortunately, these operations may cause an unnecessarily large loading capacitance to be applied to the IO driver and precharge circuit 107 and can also increase the minimum time (as measured by "tw") needed before valid data becomes available on the complementary bit lines BL and /BL.
Thus, notwithstanding the above described integrated circuit memory devices, there continues to be a need for improved integrated circuit memory devices.